On - Chip Interconnects for Multicores

......Multicore chips are entering commercial and consumer markets at a ferocious pace. They began in special-purpose, niche markets such as high-performance graphics and networking; examples are the eight-core IBM-Sony-Toshiba Cell processor, the 128core Nvidia GeForce 8800 GPU, and the 188-core Cisco Silicon Packet Processor in the CRS-1 router. Recently, multicore chips have been introduced into the generalpurpose market as well: the Sun T1 with eight cores, for example, and the recently announced Intel Xeon and AMD Barcelona with four cores. Even in the embedded system-on-chip (SoC) domain, ARM’s MPCore can be configured for up to four cores. As the core count scales up, it becomes increasingly apparent that conventional ways of interconnecting these cores, with buses and crossbars, will not work due to tight delay, power, and area budgets. A lowpower, high-bandwidth, fast on-chip communication substrate is critically needed to enable scaling to large numbers of cores. In recent years, on-chip networks have been proposed as the form such a communication substrate might take. According to Wikipedia, an on-chip network ‘‘is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches.’’ In this special issue of IEEE Micro, we set out to bring readers the latest advances in the field of on-chip interconnects for multicores. We have specifically focused this special issue on novel on-chip networks realized on actual silicon. Part of our motivation in choosing this focus is to showcase a few silicon prototypes of on-chip networks being used in multicore processors and SoCs; the other part is to bring to attention the implementation issues facing architects and designers. The first six articles in this special issue gather insights and experiences gained from the design of on-chip interconnects for multicores spanning a fairly diverse spectrum in terms of both target market and architecture: These chips’ target domains range from special-purpose processors to general-purpose computing to embedded multiprocessor SoCs. In the architectural context, they range from compositions of heterogeneous blocks of complex macro IPs to a sea of homogeneous units as simple as a functional unit. The next two articles delve into the design infrastructure support for on-chip networks, while our last article summarizes the grand research challenges for realizing next-generation on-chip networks and multicores.